The present invention relates generally to the field of semiconductor devices, and more particularly to the formation of strained fins on relaxed silicon-germanium (SiGe).
Field-effect transistors (FETs) can be semiconductor devices fabricated on a bulk semiconductor substrate or on a silicon-on-insulator (SOI) substrate. FET devices generally consist of a source, a drain, a gate, and a channel between the source and the drain. The gate is separated from the channel by a thin insulating layer, typically of silicon oxide, called the gate oxide. A voltage applied between the source and the gate induces an electric field that modulates the conductivity of the channel between the source and the drain thereby controlling the current flow between the source and the drain. Current integrated circuit designs use complementary metal-oxide-semiconductor (CMOS) technology that use complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field-effect transistors (MOSFETs) for logic functions.
Silicon-germanium (SiGe) is a general term for the alloy Si1-xGex, which consists of any molar ratio of silicon (Si) and germanium (Ge). SiGe can be used as a semiconductor material in integrated circuits as a strain-inducing layer for CMOS transistors. SiGe is manufactured on silicon wafers using conventional silicon processing toolsets.